(a) Fields of the Invention
The present invention relates to semiconductor devices which are provided with capacitor elements of three-dimensionally stacked structures employing dielectric films of dielectric materials as capacitor insulating films, and to methods for fabricating such devices.
(b) Description of Related Art
In development of ferroelectric memory devices, those of planar structures having small capacities of 1 to 64 kbit start being produced in volume. Recently, the center of development of the ferroelectric memory devices has been shifting to those of stack structures having large capacities of 256 kbit to 4 Mbit. In the ferroelectric memory devices of stack structures, a contact plug electrically connected to a semiconductor substrate is arranged immediately below a capacitor lower electrode, which reduces their cell sizes to improve their packing densities.
The trend in the ferroelectric memory devices toward miniaturization will advance in the future. With this advancement, it becomes difficult for flat-type capacitor elements to secure the quantity of electric charge necessary for memory operation, so that capacitor elements of three-dimensionally stacked structures are required which include so-called three-dimensional capacitor elements. In order to realize the capacitor elements of three-dimensionally stacked structures, it is necessary to form a dielectric film and a capacitor upper electrode with good coverage on a capacitor lower electrode of an increased surface area having the shape of a step. Conventionally, the capacitor lower electrode, the dielectric film, and the capacitor upper electrode are formed in a concave hole using a CVD method, thereby realizing the capacitor element of a three-dimensionally stacked structure (see, for example, Japanese Unexamined Patent Publication No. 2003-7859 (page 8 and FIG. 5)).
Hereinafter, the structure of a conventional semiconductor device of a three-dimensionally stacked structure having a capacitor element will be described with reference to FIG. 10.
Referring to FIG. 10, on a semiconductor substrate 100, a first interlayer insulating film 103 is formed which is composed of an oxide film 101 and a first anti-reflection film 102 of a nitride film (a SiON film). A polysilicon film 104 and first and second barrier metal films 105 and 106 are disposed in the first interlayer insulating film 103. The polysilicon film 104 is formed in a lower portion of a storage contact hole reaching an active region (not shown) of the semiconductor substrate 100, and the first and second barrier metal films 105 and 106 are formed on the polysilicon film 104 and in an upper portion of the storage contact hole. The polysilicon film 104 is formed by a chemical vapor deposition method (a CVD method). During a high-temperature thermal treatment in an oxygen atmosphere, oxygen diffuses through a storage electrode to induce oxidation of polysilicon at the interface between a polysilicon plug of the polysilicon film 104 and the storage electrode. The first and second barrier metal films 105 and 106 serve to prevent this induction.
On the first interlayer insulating film 103, a second interlayer insulating film 110 is formed which is made of an etch stop film 107, an oxide film 108, and a second anti-reflection film 109. A capacitor lower electrode 111, a first BST thin film 112, a second BST thin film 113, and a capacitor upper electrode 114 are sequentially disposed in the second interlayer insulating film 110. The capacitor lower electrode 111 with a thickness of 5 to 50 nm is formed in a storage node hole by a CVD method. The first BST thin film 112 is formed by an ALD (atomic layer deposition) method. The second BST thin film 113 is formed by a CVD method. The capacitor upper electrode 114 is formed by a CVD method or a sputtering method. Note that the capacitor upper electrode 114 and the capacitor lower electrode 111 constitute a storage electrode.
As shown above, the conventional semiconductor device includes the capacitor element having the three-dimensionally stacked structure of a concave-shaped three-dimensional configuration, thereby realizing a miniaturized, highly-integrated dielectric memory device.